The present invention relates to application specific integrated circuit (ASIC) designs. More particularly, the present invention relates to method and system for implementing an incremental change to an existing circuit design.
When an existing ASIC design needs fixes and/or upgrades, such fixes and/or upgrades are typically implemented in the resistor-transfer-level (RTL) design and re-synthesized into a new netlist. That is, a high-level circuit description is converted (synthesized) into a list of logic gates and their interconnections (netlist). Then, a new layout is created based on the new RTL floor planning, a new mask set is built in accordance with the new layout, and finally the new revision of ASIC design is manufactured in a foundry (or xe2x80x9cfabxe2x80x9d). However, this re-designing process is costly, as a new mask set can be cost more than $100,000. This is also time-consuming, since a new run through a new layout and fabrication thereof can take three months.
A xe2x80x9cfocused ion beam (FIB)xe2x80x9d approach is also available to make changes to an existing ASIC design. The FIB technique cuts metal layers at the top levels and makes edits. Although FIBs are quick, changes can be made by FIBs are limited, expensive, and typically unreliable. Thus, FIB approach is best suited to xe2x80x9ctrying out a fixxe2x80x9d situations before committing to production of a silicon substrate with a new layout.
The xe2x80x9cbackfill gatexe2x80x9d approach is established in a recent generation of ASIC technology, for example, cell-based xe2x80x9csystem-on-a chip (SOC)xe2x80x9d solutions where a multiple circuit cell (or multiple circuit core) system is formed on a single chip. In this approach, units are disposed or xe2x80x9csprinkledxe2x80x9d in unused gaps between cells/cores in a standard cell layout. A xe2x80x9cunitxe2x80x9d typically includes 2-4 transistors, and logic gates can be made from such units. The die size does not change by disposing additional units. Since such units are xe2x80x9cfree,xe2x80x9d i.e., not used in the standard circuit design, they can be programmed to be certain kinds of gates (backfill gates) so as to add or change certain functions of the standard/existing circuit design. Thus, after an ASIC is built, if there is a need for a small change (or fix) to the netlist, the backfill gates can be used to implement the change. Since the backfill gates are interconnected at the metal layers, the fix can be done with only changes at the metal layers. ASIC design tools can be used for programming the backfill gates and creating new interconnections. Thus, the implementation of a new ASIC design can be done through a fast (typically a week) and inexpensive metalization process in a foundry.
A typical unit size is 9.45 micron meter (xcexcm) tall by 3.15 xcexcm wide in a current process technology with drawn gate length of 0.18 xcexcm (effective gate length of 0.13 xcexcm). There are typically tens of thousands of multi-unit sites on a system-on-a-chip (SOC) design with a multi-million gate layout. The units can be programmed at the metal layer level to be many kinds of logic gates, such as INV, FDI, AOI, etc. Up to 30 different cells are supported by these backfill gates.
However, since the backfill gate approach utilizes changes to the gate structure, editing (change to the circuit design) is done at the netist gate level. Such gate-level change is tedious, and typically constrained to small changes, such as less than a hundred gates. In addition, functions implemented is limited to definition at the gate level, and thus typically complex functions cannot be implemented. Furthermore, the implemented backfill gates typically use multi-unit sites, i.e., contiguous unit sites. Since such multi-unit sites can be significantly distributed over the free area or gap of circuit cell/core design, implementing a number of backfill gates would cause congestion to the cell/core layout.
Accordingly, it would be desirable to provide a method and system for implementing an incremental change and/or sufficient functionality to an exiting ASIC design without causing layout congestion in a cost effective and speedy manner.
A method implements a change to a circuit design for a system formed on a semiconductor chip, the circuit design including at least one circuit core. The method includes providing in the circuit design at least one field programmable gate array (FPGA) core, extracting an incremental change to the circuit design by comparing a new resister-transfer-level (RTL) design and an old RTL design for the system, synthesizing the incremental change into a netlist for the at least one FPGA core, generating new metal layer interconnections so as to provide an input and an output for the at least one FPGA core in accordance with the incremental change, and programming the at least one FPGA core in accordance with the netlist. The at least one FPGA core is provided in an otherwise unused area of the chip.